Very-large-scale integration (VLSI) is a method of producing an integrated circuit having a very large number of transistors. Complementary metal-oxide-semiconductor (CMOS) is one technique for making integrated circuits such as microprocessors, memory, and digital logic circuits. Many digital logic circuits are implemented using p-type metal-oxide-semiconductor logic (PMOS) and n-type metal-oxide-semiconductor logic (NMOS) which respectively use p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs).
Typical synchronous digital logic circuits employ a clock signal to synchronize circuit actions. A typical clock signal takes the form of a square wave having a fixed duty cycle and frequency, wherein the duty cycle designates the ratio of the pulse width to the pulse period, and a clock pulse designates a single period of the square wave. Circuits synchronized to the clock signal respond to one or more “transition edges”, which may include either the rising edge, the falling edge, or both the rising and falling edges of the clock signal square wave. When a circuit is responsive to both the rising and falling edges, it is said to operate at a double data rate (DDR).
A delay line is a common design technique used to adjust clock or data edges in a digital circuit. A delay line is typically a regular structure comprising a chain of delay elements such as buffers. The signal is delayed by the length of the delay element thus enabling adjustment of the transition edge or edges to the desired timing window. Usually, the amount of adjustment is process, voltage, and temperature dependent, and therefore delay lines are sometimes programmable wherein the effective number of delay elements in the chain can be adjusted via external controls. The length of a delay line may be expressed in terms of the number of delay elements engaged, or “delay taps”.
Duty cycle distortion (DCD) is a variance between the duty cycle of a clock pulse at the destination as compared to the duty cycle at the source. DCD occurs when the propagation delay of the rising edge is different from the propagation delay of the falling edge. DCD can be a result of aging including a degradation of device performance over time due to effects such as electro-migration (EM) or negative bias temperature instability (NBTI). The speeds of aging for PMOS and NMOS transistors are non-symmetrical and are dependent of the state of the transistors. For example, a metal-oxide-semiconductor (MOS) ages faster when it is “on” than when it is “off”.
Duty cycle distortion is a concern when the delay line is used on a clock signal and both rising and falling edges are used, as in a double data rate interface. In such a case, a delay line is typically used to adjust the clock edges to align with data edges within the budgeted timing window. If DCD is too large (i.e., propagation delay of the rising edge is very different from that of falling edge), it may not be possible to align both rising and falling edges of the clock to data. In order to meet the timing specification, DCD must be minimized.
A single delay element in a delay line can be designed with minimal DCD—that is, the propagation delay of a rising edge is equal to the propagation delay of a falling edge within predefined tolerances—and is thus said to be balanced, for a particular process corner (meaning an extreme of possible circuit fabrication parameters). It is, however, difficult to maintain minimal DCD across all process corners. For example, if a delay element is balanced in the slow-slow (SS) or fast-fast (FF) process corner, DCD usually increases in the fast-slow (FS) or slow-fast (SF) process corners. Furthermore, DCD can accumulate and become very large as the delay line becomes longer. For example, a 0.5 picosecond DCD in a single delay element can add up to hundreds of picoseconds when the delay line is hundreds of elements long.
Moreover, due to the non-symmetrical nature of the aging effect for PMOS and NMOS transistors, a perfectly balanced delay line may still develop DCD over time.
It remains desirable, therefore, to develop improved techniques for reducing duty cycle distortion in digital circuit clock signal delay lines.